Technical Field
The present invention relates to a pixel structure and a fabrication method thereof, and in particular, to a pixel structure having a relatively low gate-drain parasitic capacitance and a low gate-source parasitic capacitance and a fabrication method thereof.
Related Art
With advances in the modern technologies, displays of various specifications have been widely applied to screens of electronic products for consumers, for example, mobile phones, notebook computers, digital cameras, Personal Digital Assistants (PDA), etc. Among the displays, liquid crystal displays (LCD) and organic electro-luminescent displays (OELD or OLED) become mainstream commodities in the market due to the advantages of being light and thin and having a low power consumption.
The process for manufacturing the LCDs and the OLEDs includes arranging an array of semiconductor elements on a substrate, and the semiconductor element includes a thin film transistor (TFT). Along with an increase in the degree of resolutions of the LCDs and the OLEDs, a proportion occupied by thin film transistors in a unit area also increases. Further, because there are overlapped regions between a gate electrode and a source electrode and between the gate electrode and a drain electrode of the thin film transistor, a ratio of a gate electrode-drain electrode parasitic capacitance and a gate electrode-source electrode parasitic capacitance (that is, Cgd and Cgs) of the thin film transistor to a storage capacitance also increases accordingly. Therefore, generally a large Resistance-Capacitance loading (RC loading) may be generated in transmission of signals when the thin film transistor is used as a transistor in a driving circuit, thereby leading to the reduction in the display quality of a display.